The present invention relates to a semiconductor memory apparatus, or more particularly to a technique effectively applicable to a cache memory built in a data processing apparatus like a microprocessor or a microcomputer.
In recent years, with the increase in the operating frequency of the microprocessor, there has been an increasing demand for a cache memory of a higher speed. In the cache memory, data are written by transmitting signals to memory cells through bit lines, and are read from the memory cells by transmitting them to an amplifier circuit through bit lines. For a cache memory of a high operating speed to be realized, therefore, it is crucial to reduce the capacity of the bit lines. Memories with a reduced capacity of bit lines include a circuit with a memory mat divided and bit lines formed in a hierarchy (hereinafter referred to as the prior art 1) disclosed in ISSCC Digest of Technical Papers, pp. 304-305, February, 1995.
The memory according to the prior art 1 comprises a memory mat with 6-transistor memory cells arranged in an array and divided into n equal parts to form n blocks. The bit lines (BL, BLB) in each block are connected with an I/O bus formed across the bank through a sense amplifier (S/A) and an I/O circuit configured in a pair with each block.
In reading data, the data read from each memory cell is transmitted to the sense amplifier (S/A) and the I/O circuit using the bit lines (BL, BLB) thereby to output data to an I/O bus. Data are written in the memory cells by transmitting the data in the I/O bus to the bit lines (BL, BLB) using the sense amplifier (S/A) and the I/O circuit.